RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x010: Microprocessor Cell Buffer Interrupt Control and Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
EXTCRCERRI
EXTRDYI
X
X
X
X
0
0
0
0
INSOVRI
INSRDYI
EXTCRCERRE
EXTRDYE
INSOVRE
R
R/W
R/W
R/W
R/W
INSRDYE
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for the interrupt enables to take effect.
INSRDYE:
The INSRDYE bit allows the generation of an interrupt when an Insert FIFO
becomes available. When INSRDYE is set to logic 1, the INTB output is
asserted low when the INSRDYI bit is logic 1.
INSOVRE:
The INSOVRE bit controls the generation of an interrupt upon an overflow of
an insert buffer. When INSOVRE is set to logic 1, the INTB output is
asserted low when the INSOVRI bit is logic 1.
EXTRDYE:
The EXTRDYE bit allows the generation of an interrupt when an Extract FIFO
becomes ready. When EXTRDYE is set to logic 1, the INTB output is
asserted low when the EXTRDYI bit is logic 1.
EXTCRCERRE:
The EXTCRCERRE bit controls the generation of the interrupt upon a CRC-
32 error. When EXCRCERRE is set to logic 1, the INTB output is asserted
low when the EXTCRCERRI bit is logic 1.
INSRDYI:
The INSRDYI bit provides a status of the Insert FIFOs Ready Interrupt. This
bit is set to logic 1 when one of the Insert FIFOs becomes ready to accept a
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
73
PMC [ PMC-SIERRA, INC ]
