RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
11.1 RAM Built-In-Self-Test
The S/UNI-VORTEX contains built-in-self-test (BIST) circuitry for production
testing of the device. A subset of the functionality is available for in situ
screening against damage during handling and board manufacture.
The tests are controlled through the microprocessor port. The only other signals
involved are the TCLK and RCLK inputs. The following procedure tests the
numerous RAMs simultaneously:
1. Hold TCLK and RCLK low.
2. Set the RESET bit of the Master Reset and Identity register (0x000) to
logic 1 to place the device in a known state.
3. Write the following register locations to select the test mode and initialize
the BIST circuitry:
Write 0x01 to 0x2nC, 0x3mC where n = 8, 9, A…F; m = 0,1,2…7
Write 0x02 to 0x2nD, 0x3mD
Write 0x55 to 0x2nE, 0x3mE
These registers do not have default values and must be written.
4. Clear the RESET bit of the Master Reset and Identity register (0x000) to
logic 0.
5. Set the IOTST bit of the Master Test register (0x200) to logic 1. This
activates the BIST test mode.
6. Start toggling the TCLK and RCLK inputs at up to their specified maximum
frequency. The two clocks must be frequency locked.
7. After exactly 16384 clock cycles read the following registers and compare
against the expected data. Any discrepancies represent a test failure.
Letting the test run indefinitely simply causes the test sequences to be
repeated.
Expected
A[9:0]
0x007
D[7:0]
xxx0xx11 (Ensures TCLK and RCLK
have toggled.)
xxxx001x
0x2nE, 0x3mE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
120
PMC [ PMC-SIERRA, INC ]
