RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x09C, 0x0BC, 0x0DC, 0x0FC, 0x11C, 0x13C, 0x15C, 0x17C:
Upstream Link FIFO Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
Reserved
FIFORST
X
X
X
X
X
X
0
R/W
R/W
0
FIFORST:
The FIFORST bit is used to reset the upstream FIFO for a link. When
FIFORST is set to logic 0, the FIFO operates normally. When FIFORST is
set to logic 1, all the FIFOs are immediately emptied and ignore writes.
While the FIFO is reset the flow control information sent to the far end (via
the LVDS link) indicates “buffer full or unavailable”. The FIFO remains
empty until logic 0 is written to FIFORST. To prevent unstable behavior
during cell format configuration, FIFORST should be left asserted while
changing the cell format or length.
Assertion of the FIFORST bit may result in a corrupted cell being
transferred across the receive SCI-PHY/Any-PHY bus if there is currently
active traffic on the associated high-speed serial link. Traffic for the other
seven serial links not associated with the FIFORST bit will not be affected.
There is an upstream FIFO for each of the LVDS links. The eight FIFOs
feed cells one at a time into the upstream Utopia or Any-PHY bus.
Therefore, a reset on one of these FIFOs may cause the current cell
being transferred over the bus to be corrupted. The specific conditions
that will lead to corruption are as follows:
1. There must be at least one user cell in the upstream FIFO being
reset. This cell will have arrived sometime previously over the
LVDS.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
114
PMC [ PMC-SIERRA, INC ]
