RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x088, 0x0A8, 0x0C8, 0x0E8, 0x108, 0x128, 0x148, 0x168:
Receive High-Speed Serial FIFO Overflow
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
UPFOVRI
FOVRI
Unused
Unused
UPFOVRE
FOVRE
X
X
X
X
X
X
0
R
R
R/W
R/W
0
The status bits in this register provide an indication of cell loss due to over flows
in the Upstream Link FIFOs. Generally, the FOVRI and UPFOVRI status bits
should never be asserted; their assertion would indicate that the flow control
protocol is being ignored.
FOVRE:
The FOVRE bit enables the assertion of the INTB output upon FOVRI
transitioning high. When FOVRE is set to logic 1, the interrupt is enabled.
UPFOVRE:
The UPFOVRE bit enables the assertion of the INTB output upon UPFOVRI
transitioning high. When UPFOVRE is set to logic 1, the interrupt is enabled.
FOVRI:
The FOVRI bit is set to logic 1 when a valid cell is lost due to an over flow of
the associated Upstream Link FIFO. This bit is reset immediately after a read
to this register.
UPFOVRI:
The UPFOVRI bit is set to logic 1 when a valid control channel cell is lost due
to an over flow of the associated Upstream Microprocessor Cell Buffer. This
bit is reset immediately after a read to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
PMC [ PMC-SIERRA, INC ]
