RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x082, 0x0A2, 0x0C2, 0x0E2, 0x102, 0x122, 0x142, 0x162:
Receive High-Speed Serial Interrupt Enables
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
HCSE
XFERE
OCDE
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CELLERRE
ACTE
LCDE
LOSE
These registers allow changes in the Receive High-Speed Serial Cell Filtering
Configuration/Status register bits, HCS errors and counter transfers to cause
assertion low the INTB output.
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for the interrupt enables to take effect.
LOSE:
The LOSE bit enables the generation of an interrupt upon a change in the
Loss of Signal state. When LOSE is set to logic 1, the interrupt is enabled.
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the
LCD (Loss of Cell Delineation) state. When LCDE is set to logic 1, the
interrupt is enabled.
ACTE:
The ACTE bit enables the generation of an interrupt due to a change in the
ACTV register bit. When ACTE is set to logic 1, the interrupt is enabled.
CELLERRE:
The CELLERRE bit enables the generation of an interrupt due to a non-zero
remainder of the CRC-8 protecting the entire cell. When CELLERRE and
CELLCRC are set to logic 1, the interrupt is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
90
PMC [ PMC-SIERRA, INC ]
