RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
LIST OF FIGURES
FIG. 1 TYPICAL TARGET APPLICATION........................................................... 5
FIG. 2 THREE STAGE MULTIPLEX ARCHITECTURE....................................... 7
FIG. 3 CLOCK AND DATA PHY INTERFACE ..................................................... 8
FIG. 4 S/UNI-DUPLEX TO S/UNI-DUPLEX APPLICATIONS............................ 10
FIG. 5 S/UNI-DUPLEX TO S/UNI-DUPLEX PROTECTION SWITCHING........ 10
FIG. 6 EIGHT BIT SCI-PHY/UTOPIA/ANY-PHY CELL FORMAT...................... 56
FIG. 7 SIXTEEN BIT SCI-PHY/UTOPIA/UTOPIA CELL FORMAT.................... 57
FIG. 8 CELL DELINEATION STATE DIAGRAM................................................ 59
FIG. 9 HIGH-SPEED SERIAL LINK DATA STRUCTURE ................................. 62
FIG. 10 DATAPATH LOOPBACK ...................................................................... 66
FIG. 11 MICROPROCESSOR CELL FORMAT................................................. 79
FIG. 12 INPUT OBSERVATION CELL (IN_CELL) .......................................... 179
FIG. 13 OUTPUT CELL (OUT_CELL)............................................................. 180
FIG. 14 BIDIRECTIONAL CELL (IO_CELL).................................................... 180
FIG. 15 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ....... 181
FIG. 16 BOUNDARY SCAN ARCHITECTURE ............................................... 197
FIG. 17 TAP CONTROLLER FINITE STATE MACHINE................................. 199
FIG. 18 SCI-PHY INTERFACE, INPUT BUS SLAVE TRANSFER TIMING..... 203
FIG. 19 SCI-PHY INTERFACE, INPUT BUS MASTER TRANSFER TIMING. 204
FIG. 20 ANY-PHY INTERFACE, INPUT BUS SLAVE TRANSFER TIMING.... 205
FIG. 21 SCI-PHY INTERFACE, OUTPUT BUS SLAVE TRANSFER TIMING. 206
FIG. 22 SCI-PHY INTERFACE, OUTPUT BUS MASTER TRANSFER TIMING
207
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
vii
PMC [ PMC-SIERRA, INC ]
