RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Ball
Name
Type
No. Function
High Speed LVDS Links
IADDR[4]
IADDR[3]
IADDR[2]
IADDR[1]
IADDR[0]
(Cont’d)
As a bus slave device (either SCI-PHY or Any-
PHY), the S/UNI-DUPLEX can be configured to be
restricted to a subset of the logical channel address
range. In this case, device polling or selection will
occur when the logical channel addressed by
IADDR[4:0] is inside the address range specified by
ICAEN[31:0] of the Input Cell Available Enable
registers.
The IADDR[4:0] bus is updated or sampled on the
rising edge of IFCLK.
These signals are only active if the SCIANY input is
a logic high.
IAVALID
I/O
B6 The Input Port Address Valid (IAVALID) pin
indicates that the IADDR[4:0] bus is asserting a
valid PHY address for polling purposes.
As a SCI-PHY/Utopia bus master (IMASTER = 1,
IANYPHY = 0) IAVALIV is an output. When IAVALID
is deasserted, the IADDR[4:0] bus is set to 0x1F as
defined by the Utopia L2 bus standard. therefore
use of IAVALID is not necessary when less than 32
PHY devices are being polled.
As a bus slave (IMASTER = 0) IAVALID is an input
used to control the ICA output. IAVALID is active
highin SCI-PHY/Utopia mode (IANYPHY = 0) and
active low in Any-PHY mode (IANYPHY = 1). The
ICA output is only driven when IAVALID is sampled
active. If IAVALID is sampled inactive, ICA becomes
high impedance. The S/UNI-DUPLEX supports
polling in contiguous cycles if IAVALID is held
active.
ICA is delayed by an additional IFCLK
cycle.IAVALID is sampled or updated on the rising
edge of IFCLK.
This signal is only active if the SCIANY input is a
logic high.
Parallel Bus - Output
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
27
PMC [ PMC-SIERRA, INC ]
