Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
2.2.2 Phase Aligners
Phase aligners are used to allow for extended device separation. The technique used is a clock
recovery mechanism that requires only the switch fabric to be frequency synchronous. A master
clock is distributed to all devices associated with the switch fabric, and the phase of the clock at
each interface is dynamically adjusted to account for skew introduced to the signals. The phase
aligner circuitry for each interface responds to the cell start and feedback signals, which contain a
high number of transitions to ensure accurate phase adjustment of the clock for data and signal
sampling.
2.2.3 UTOPIA Interface
The QRT’s UTOPIA interface implements the ATM Forum standardized 16-bit, Level 2 configu-
ration, which supports up to 31 Virtual Outputs (VOs) via five address bits. Up to 31 PHY or
AAL layer devices with 16-bit UTOPIA Level 2 functionality can be connected to this interface,
providing full duplex throughputs of 675 Mbps.
2.2.4 Cell Buffer SDRAM Interface
The QRT supports two Synchronous DRAM (SDRAM or SGRAM) interfaces providing up to
64K of cell buffering in both the receive and transmit directions. Each interface consists of a 32-
bit data bus, a 9-bit address bus, two chip select signals, and associated control signals. The fre-
quency of these interfaces is 100 MHz. Both Synchronous Graphic RAM (SGRAM) and SDRAM
devices are supported. Clocking for these two interfaces is provided through the device.
2.2.5 Channel RAM (CH_RAM) Interface
The QRT supports up to 16K channels through a Synchronous SRAM (SSRAM) interface. The
interface consists of a 32-bit data bus, a 16-bit address bus, and associated control signals. The
frequency of this interface is 100 MHz. Clocking for this interface is provided through the device.
2.2.6 Address Lookup RAM (AL_RAM) Interface
The QRT has data structures in the AL_RAM, including VPI/VCI address translation. The inter-
face consists of a 6-bit data bus, a 17-bit address bus, and associated control signals. The fre-
quency of this interface is 100 MHz. Clocking for this interface is provided through the device.
2.2.7 AB_RAM Interface
The QRT stores the per VC head / tail pointers and sent / dropped counters for the receive direc-
tion in the AB_RAM. Each interface consists of a 17-bit multiplexed address/data bus and associ-
ated control signals. The frequency of this interface is 100 MHz.
2.2.8 Host Processor Interface
The QRT host processor interface allows connection of a microprocessor through a multiplexed
®
32-bit address/data bus. The suggested microprocessor for this interface is the Intel i960 . The
microprocessor has direct access to all of the QRT control registers.
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PMC [ PMC-SIERRA, INC ]
