Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
11.4.1 Relationship Among the SYSCLK, SE_CLK, and the Switch Speed-Up Factor
The SE_CLK relationship with the SYSCLK is governed by the following equation.
SE_CLK = (66 ÷ 100) × SYSCLK
Thus, if SYSCLK is lowered in frequency, SE_CLK frequency must be lowered in the same pro-
portion to maintain switch fabric speed-up factor at 1.6.
Switch speed-up factor requirements are switch-topology dependent. For a detailed speed-up fac-
tor discussion, refer to the QSE (PM73488) Long Form Data Sheet.
11.4.2 The Phase Aligner SE_CLK Frequency Constraint
Phase aligners at the QRT switch fabric interfaces are designed to operate in the SE_CLK fre-
quency range of 50 MHz to 66 MHz. Phase aligners are not expected to converge beyond this fre-
quency range. If an application requires the SE_CLK to be less than 50 MHz, it should operate the
device with the phase aligners turned off.
11.4.3 The SYSCLK DRAM Refresh Constraint
In normal operating mode, the QRT refreshes one row of DRAM per cell time. A cell time is
defined as the sum of 118 SE_CLK periods.
Cell Time = 118 × (1 ÷ SE_CLK)
A typical SGRAM requires 1024 rows to be refreshed in 17 ms. A typical SDRAM requires 2048
rows to be refreshed in 32 ms. This implies a row refresh every 15.6 µs. The SE_CLK therefore,
should never be operated below 7.552 MHz. This also implies that the SYSCLK never be oper-
ated below 11.44 MHz.
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PMC [ PMC-SIERRA, INC ]
