S/UNI®-JET Data Sheet
Released
Table of Contents
1
2
3
4
5
6
7
8
9
Features.....................................................................................................................17
Applications ...............................................................................................................21
References ................................................................................................................22
Definitions..................................................................................................................24
Application Examples ................................................................................................26
Block Diagram ...........................................................................................................28
Description.................................................................................................................29
Pin Diagram...............................................................................................................32
Pin Description...........................................................................................................34
10 Functional Description...............................................................................................54
10.1 DS3 Framer.......................................................................................................54
10.2 E3 Framer .........................................................................................................56
10.3 J2 Framer..........................................................................................................58
10.3.1 J2 Frame Find Algorithms ....................................................................59
10.4 RBOC Bit-Oriented Code Detector ...................................................................62
10.5 RDLC PMDL Receiver ......................................................................................62
10.6 PMON Performance Monitor Accumulator........................................................63
10.7 SPLR PLCP Layer Receiver.............................................................................63
10.8 ATMF ATM Cell Delineator................................................................................64
10.9 PRGD Pseudo-Random Sequence Generator/Detector ..................................65
10.10 RXCP-50 Receive Cell Processor ....................................................................66
10.11 RXFF Receive FIFO..........................................................................................68
10.12 CPPM Cell and PLCP Performance Monitor ....................................................69
10.13 DS3 Transmitter ................................................................................................69
10.14 E3 Transmitter...................................................................................................70
10.15 J2 Transmitter ...................................................................................................71
10.16 XBOC Bit Oriented Code Generator.................................................................72
10.17 TDPR PMDL Transmitter ..................................................................................72
10.18 SPLT SMDS PLCP Layer Transmitter ..............................................................73
10.19 TXCP-50 Transmit Cell Processor....................................................................74
10.20 TXFF Transmit FIFO.........................................................................................74
10.21 TTB Trail Trace Buffer.......................................................................................75
10.22 JTAG Test Access Port......................................................................................75
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
5
PMC [ PMC-SIERRA, INC ]
