S/UNI®-JET Data Sheet
Released
6
Block Diagram
Figure 3 Block Diagram
XBOC
Tx
TDPR
Tx
1/2 TTB
Tx Trail
Buffer
Tx O/H
Access
IEEE P1149.1
JTAG Test
DTCA
FEAC
HDLC
Access Port
TDAT[15.0]
TPRTY
TSOC
TPOS/TDATO
TNEG/TOHM
TCLK
TRAN
TCA
TADR[2.0]
TENB
TFCLK
PHY_ADR[2.0]
ATM8
TXFF
SPLT
Line
TXCP_50
Tx Cell
J2, E3, or DS3
Tx 4 Cell
FIFO
Transmit ATM and
PLCP Framer
Encode
Transmit Framer
Processor
System
I/F
RFCLK
RENB
RADR[2.0]
RCA
RSOC
ATMF/SPLR
Receive ATM
FRMR
RXFF
Rx 4 Cell
FIFO
RCLK
RPOS/RDATI
RNEG/RLCV/ROHM
RXCP_50
Rx Cell
Line
J2, E3, or DS3
Receive Framer
and PLCP Framer
Decode
Processor
RPRTY
RDAT[15.0]
DRCA
CPPM
PLCP/cell
Performance
Monitor
RBOC
Rx
RDLC
PMON
1/2 TTB
Rx O/H
Access
Microprocessor
Interface
Rx
Perfor.
Rx Trail
Buffer
FEAC
HDLC
Monitor
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
28
PMC [ PMC-SIERRA, INC ]
