PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name
Type
Pin No. Function
RGAPCLK[4] Output W13
Framer Recovered Gapped Clock
(RGAPCLK[4:1]). RGAPCLK[4:1] is valid
when the S/UNI-QJET is configured as a
DS3, E3, or J2 framer for non-ATM
applications by setting the FRMRONLY bit
in the S/UNI-QJET Configuration 1
Register and the RXGAPEN bit in the
S/UNI-QJET Configuration 2 Register.
RGAPCLK[3]
RGAPCLK[2]
RGAPCLK[1]
U10
V7
U5
RGAPCLK[4:1] is the recovered clock and
timing reference for RDATO[4:1].
RGAPCLK[4:1] is held high for bit
positions which correspond to overhead.
LCD[4]
LCD[3]
LCD[2]
LCD[1]
Output Y14
Loss of Cell Delineation (LCD[4:1]).
LCD[4:1] is an active high signal which is
asserted while the ATM cell processor has
detected a Loss of Cell Delineation defect.
The FRMRONLY bit in the S/UNI-QJET
Configuration 1 Register must be set to
logic 0 for LCD[4:1] to be valid.
W10
W7
Y4
RDATO[4]
RDATO[3]
RDATO[2]
RDATO[1]
Framer Receive Data (RDATO[4:1]).
RDATO[4:1] is valid when the S/UNI-QJET
is configured as a DS3, E3, or J2 framer
for non-ATM applications by setting the
FRMRONLY bit in the S/UNI-QJET
Configuration 1 Register.
RDATO[4:1] is the received data aligned to
RFPO/RMFPO[4:1] and ROVRHD[4:1].
RDATO[4:1] is updated on the active edge
(as set by the RSCLKR register bit) of
RSCLK[4:1] or RGAPCLK[4:1].
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 39
PMC [ PMC-SIERRA, INC ]
