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PM7346 参数 Datasheet PDF下载

PM7346图片预览
型号: PM7346
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD用户网络接口, J2 , E3 , T3 [SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3]
分类和应用: 网络接口
文件页数/大小: 419 页 / 2502 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7346 S/UNI-QJET  
DATASHEET  
PMC-960835  
ISSUE 6  
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3  
Pin Name  
Type  
Input  
Pin No. Function  
ROHM[4]  
ROHM[3]  
ROHM[2]  
ROHM[1]  
C5  
E3  
E1  
G2  
Receive Overhead Mask (ROHM[4:1]).  
When a DS1 or E1 PLCP or ATM direct-  
mapped signal is received, ROHM[4:1] is  
pulsed once per transmission frame, and  
indicates the DS1 or E1 frame alignment  
relative to the RDATI[4:1] data stream.  
When an alternate frame-based signal is  
received, ROHM[4:1] indicates the position  
of each overhead bit in the transmission  
frame.  
The RNEG/RLCV/ROHM[4:1] pin function  
selection is controlled by the RFRM[1:0]  
bits in the S/UNI-QJET Receive  
Configuration Registers, the UNI bits in the  
DS3 FRMR, E3 FRMR, or J2 FRMR  
Configuration Registers, and the PLCPEN  
and EXT bits in the SPLR Configuration  
register. RNEG[4:1], RLCV[4:1], and  
ROHM[4:1] are sampled on the rising  
edge of RCLK[4:1] by default, and may be  
enabled to be sampled on the falling edge  
of RCLK[4:1]. This sampling is controlled  
by the RCLKINV bit in the S/UNI-QJET  
Receive Configuration Registers. In  
addition, signal polarity control is provided  
by the RNEGINV bit in the S/UNI-QJET  
Receive Configuration Registers.  
RCLK[4]  
RCLK[3]  
RCLK[2]  
RCLK[1]  
Input  
A4  
F4  
F3  
G1  
Receive Clock (RCLK[4:1]). RCLK[4:1]  
provides the receive direction timing.  
RCLK[4:1] is the externally recovered  
transmission system baud rate clock that  
samples the RPOS/RDATI[4:1] and  
RNEG/RLCV/ROHM[4:1] inputs on its  
rising or falling edge.  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 25  
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