PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 002H, 102H, 202H and 302H: Datalink Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
RXDMASIG
Unused
TXDMASIG
Unused
RDLINTE
RDLEOME
TDLINTE
TDLUDRE
0
X
0
X
0
0
0
0
R/W
R/W
R/W
R/W
R/W
These registers allow software to configure the datalink options of each T1 or E1
interface.
RXDMASIG:
The RXDMASIG bit selects the internal HDLC receiver (RFDL) data-received
interrupt (INT) and end-of-message (EOM) signals to be output on the
RDLINT[x] and RDLEOM[x] pins. When RXDMASIG is set to logic 1, the
RDLINT[x] and RDLEOM[x] output pins can be used by a DMA controller to
process the datalink. When RXDMASIG is set to logic 0, the RFDL INT and
EOM signals are no longer available to a DMA controller; the signals on
RDLINT[x] and RDLEOM[x] become the extracted datalink data and clock,
RDLSIG[x] and RDLCLK[x]. In this mode, the data stream available on the
RDLSIG[x] output corresponds to the extracted facility datalink for T1-ESF, or
to the extracted timeslot 0 National bits or timeslot 16 for E1.
TXDMASIG:
The TXDMASIG bit selects the internal HDLC transmitter (XFDL) request for
service interrupt (INT) and data underrun (UDR) signals to be output on the
TDLINT[x] and TDLUDR[x] pins. When TXDMASIG is set to logic 1, the
TDLINT[x] and TDLUDR[x] output pins can be used by a DMA controller to
service the datalink. When TXDMASIG is set to logic 0, the XFDL INT and
UDR signals are no longer available to a DMA controller; the signals on
TDLINT[x] and TDLUDR[x] become the serial datalink data input and clock,
TDLSIG[x] and TDLCLK[x]. In this mode an external controller is responsible
for formatting the data stream presented on the TDLSIG[x] input to
correspond to the facility datalink in T1-ESF, or to the extracted timeslot 0
National bits or timeslot 16 for E1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
