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PM7344 参数 Datasheet PDF下载

PM7344图片预览
型号: PM7344
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN QUAD T1 / E1 MULTI -PHY用户网络接口设备 [SATURN QUAD T1/E1 MULTI-PHY USER NETWORK INTERFACE DEVICE]
分类和应用: 网络接口
文件页数/大小: 293 页 / 1101 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7344 S/UNI-MPH  
DATA SHEET  
PMC-950449  
ISSUE 6  
MULTI-PHY USER NETWORK INTERFACE  
high causes the S/UNI-MPH to drive the data bus and holding the CSB pin  
low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The  
DBCTRL bit is used to measure the drive capability of the data bus driver  
pads.  
IOTST:  
The IOTST bit is used to allow normal microprocessor access to the test  
registers and control the test mode in each block in the S/UNI-MPH for board  
level testing. When IOTST is a logic 1, all blocks are held in test mode and  
the microprocessor may write to a block's test mode 0 registers to manipulate  
the outputs of the block and consequently the device outputs (refer to the  
"Test Mode 0 Details" in the "Test Features" section).  
HIZIO,HIZDATA:  
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-MPH .  
While the HIZIO bit is a logic 1, all output pins of the S/UNI-MPH except the  
data bus are held in a high-impedance state. The microprocessor interface is  
still active. While the HIZDATA bit is a logic 1, the data bus is also held in a  
high-impedance state which inhibits microprocessor read cycles.  
12.1 Test Mode 0  
In Test Mode 0, the S/UNI-MPH allows the logic levels on the device inputs to be  
read through the microprocessor interface, and allows the device outputs to be  
forced to either logic level through the microprocessor interface (except for  
RDAT[7:0], RSOC, RXPRTY, and RCA).  
To enable Test Mode 0, 00H should be written to every address in the Test  
Register Memory Map (400H to 7FFH) and then the IOTST bit in the Master Test  
Register (Register 00CH) should be set to logic 1. Some particular I/O require  
certain configuration bits to be set properly for Test Mode 0 operation to work.  
These configuration requirements are detailed in the notes accompanying the  
following address maps.  
Reading the following address locations returns the values for the indicated  
inputs to the D[7:0] bits:  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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