PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Register 00CH: Revision/Chip ID/Global Monitoring Update
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
R
R
R
R
R
R
RESET
TYPE[2]
TYPE[1]
TYPE[0]
TIP
ID[2]
ID[1]
ID[0]
0
1
0
1
0
0
0
0
RESET:
The RESET bit allows software to asynchronously reset the S/UNI-MPH. The
software reset is equivalent to setting the RSTB input pin low. When a logic 1
is written to RESET, the S/UNI-MPH is reset. When a logic 0 is written to
RESET, the reset is removed. The RESET bit must be explicitly set and
cleared by writing the corresponding logic value to this register.
TYPE[2:0]:
The TYPE[2:0] bits allow software to identify this device as the S/UNI-MPH
member of the S/UNI family of products.
TIP:
The TIP bit is set to a logic one when any value with Bit 7 set to logic 0 is
written to this register. Such a write initiates an accumulation interval transfer
and loads all the performance meter registers in the PMON, RXCP, and
TXCP blocks. TIP remains high while the transfer is in progress, and is set to
a logic zero when the transfer is complete. TIP can be polled by a
microprocessor to determine when the accumulation interval transfer is
complete. Note that the transmit and receive line side clocks must be
toggling for TIP to be cleared.
ID[2:0]:
The ID[2:0] bits allows software to identify the version level of the S/UNI-
MPH.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
92
PMC [ PMC-SIERRA, INC ]
