PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 00AH, 10AH, 20AH and 30AH: Diagnostics and FIFO Parity
Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
TEVEN
REVEN
PAYLB
LINELB
Unused
DIALB
0
0
0
0
X
0
0
0
R/W
R/W
R
TPERRE
TPERRI
These registers allow software to enable the diagnostic mode of each interface
and the control the fifo parity functions.
TEVEN:
The TEVEN bit selects the type of parity calculated and compared on the
transmit synchronous FIFO interface. When TEVEN is logic 1, even parity is
calculated across the TDAT[7:0] bus and compared to the incoming parity bit
on TXPRTY. If there is a mismatch, the parity error indication, TPERRI, is
forced to logic 1, and an interrupt is generated, if enabled. When TEVEN is
logic 0, odd parity is calculated across TDAT[7:0] and compared to TXPRTY.
Again, a parity error is indicated if there is a mismatch.
REVEN:
The REVEN bit selects the type of parity calculated and output on the receive
synchronous FIFO interface. When REVEN is logic 1, even parity is
calculated across the RDAT[7:0] bus and indicated on the outgoing parity bit,
RXPRTY. When REVEN is logic 0, odd parity is calculated across RDAT[7:0]
and indicated on RXPRTY.
PAYLB:
When the T1 or E1 format is selected, the PAYLB bit selects payload
loopback. When PAYLB is set to logic 1, the received data output from the
FRMR is internally connected to the transmit data input of the TRAN. The
framing bit (T1 format) or timeslots 0 and 16 (E1 format) are reinserted by the
TRAN prior to transmission. When PAYLB is set to logic 0, the payload
loopback mode is disabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
88
PMC [ PMC-SIERRA, INC ]
