PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 000H, 100H, 200H and 300H: Receive Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
WORDERR
CNTNFAS
RXDMAGAT
Unused
Unused
Unused
MODE[1]
MODE[0]
0
0
0
X
X
X
0
0
R/W
R/W
These registers are used to configure the receive interfaces of the S/UNI-MPH.
WORDERR:
When the E1 format is enabled, the WORDERR bit determines how frame
alignment signal (FAS) errors are reported. When WORDERR is logic 1, one
or more errors in the seven bit FAS word results in a single framing error
count. When WORDERR is logic 0, each error in a FAS word results in a
single framing error count.
CNTNFAS:
When the E1 format is enabled, the CNTNFAS bit determines whether non-
frame alignment signal (NFAS) errors are reported. When the CNTNFAS bit
is a logic 1, a zero in bit 2 of time slot 0 of NFAS frames results in an
increment of the framing error count. If WORDERR is also a logic 1, the
word is defined as the eight bits comprising the FAS pattern and bit 2 of time
slot 0 of the next NFAS frame. When the CNTNFAS bit is a logic 0, only
errors in the FAS affect the framing error count.
RXDMAGAT:
The RXDMAGAT bit selects the gating of the RDLINT[x] output with the
RDLEOM[x] output when the internal HDLC receiver is used with DMA. When
RXDMAGAT is set to logic 1, the RDLINT[x] DMA output is gated with the
RDLEOM output so that RDLINT is forced to logic 0 when RDLEOM is logic
1. When RXDMAGAT is set to logic 0, the RDLINT[x] and RDLEOM[x]
outputs operate independently.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PMC [ PMC-SIERRA, INC ]
