PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
If there are more than five consecutive ones in the raw transmit data or in the
CRC data, a zero is stuffed into the serial data output. This prevents the
unintentional transmission of flag or abort characters.
Abort characters can be continuously transmitted at any time by setting a control
bit. During transmission, an underrun situation can occur if data is not written to
the Transmit Data Register before the previous byte has been depleted. In this
case, an abort sequence is transmitted, and the controlling processor is notified
via the TDLUDR signal. Optionally, the interrupt and underrun signals can be
independently enabled to also generate an interrupt on the INTB output,
providing a means to notify the controlling processor of changes in the XFDL
operating status.
When the internal HDLC transmitter is disabled, the serial data to be transmitted
in the facility data link or in timeslot 16 or timeslot 0 can be input on the
TDLSIG[x] pin timed to the clock rate output on the TDLCLK[x] pin.
9.14 Digital Transmit Interface (DTIF)
The Digital Transmit Interface provides control over the various output options
available on the multifunctional digital transmit pins TDP/TDD and TDN/TOHP.
When configured for dual-rail output, the multifunctional pins become the TDP
and TDN outputs. These outputs can be formatted as either return-to-zero (RZ)
or non-return-to-zero (NRZ) signals and can be updated on either the rising or
falling edge of TCLKO. When the interface is configured for single-rail output, or
when the T1/E1 framers are bypassed, the multifunctional pins become the TDD
and TOHO outputs, which can be enabled to be updated on either the rising or
falling TCLKO edge. When the T1/E1 framers are bypassed, arbitrary bit rate
interfaces, such as the 6.312 Mbit/s J2 rate may be supported.
9.15 Digital Jitter Attenuator
The Digital Jitter Attenuator (DJAT) function is contained in the DTIF block and is
used to attenuate jitter in the transmit clock when required. The DJAT function is
normally enabled if the S/UNI-MPH is loop-timed from RCLKO, or if the transmit
clock (TCLKI) requires jitter attenuation before transmission. The block receives
jittered data from the TRAN block and stores this data in a FIFO. The data
emerges from the DJAT timed to the jitter attenuated clock, TCLKO.
The DJAT generates the jitter-free 1.544/2.048 MHz TCLKO clock by adaptively
dividing the 24x XCLK input according to the phase difference between the
generated TCLKO and the input data clock to DJAT (TCLKI or RCLKO). Phase
variations in the input clock with a jitter frequency above 8.8 Hz (for the E1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
49
PMC [ PMC-SIERRA, INC ]
