PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
3. These clock tolerances assume that the line clock tolerance is ±130ppm for
T1 and ±50ppm for E1.
4. TCLKI can be a jittered clock signal subject to the instantaneous frequencies
corresponding to the minimum and maximum high and low TCLKI pulse
widths shown.
5. High pulse width is measured from the 1.4 Volt points of the rise and fall
ramps. Low pulse width is measured from the 1.4 Volt points of the fall and
rise ramps.
6. Guaranteed by design for nominal XCLK frequencies. May not be production
tested.
Notes on Output Timing:
7. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
8. Output propagation delays are measured with a 50 pF load on the outputs
except on D[7:0] where the load is 100 pF.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
273
PMC [ PMC-SIERRA, INC ]
