PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 048H, 148H, 248H and 348H: PMON Control/Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
INTE
X
X
X
X
X
0
R/W
R
R
INT
OVR
0
0
These registers enable an interrupt to be generated on the INTB pin whenever
counter data is transferred into the holding registers. The configuration register
also contains status information as to whether the holding registers have been
overrun.
INTE:
The INTE bit controls the generation of a microprocessor interrupt when the
transfer clock has caused the counter values to be stored in the holding
registers. A logic 1 bit in the INTE position enables the generation of an
interrupt. A logic 0 bit in the INTE position disables the generation of an
interrupt.
INT:
The INT bit is the current status of the interrupt signal. A logic 1 in this bit
position indicates that a transfer has occurred. A logic 0 indicates that no
transfer has occurred. The interrupt is cleared (acknowledged) by reading
this register.
OVR:
The OVR bit is the overrun status of the holding registers. A logic 1 in this bit
position indicates that a previous interrupt has not been acknowledged before
the next transfer clock has been issued and that the contents of the holding
registers have been overwritten. A logic 0 indicates that no overrun has
occurred. The OVR bit is cleared by reading this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
158
PMC [ PMC-SIERRA, INC ]
