PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 035H, 135H, 235H and 335H: XFDL Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
INT
X
X
X
X
X
X
1
R
R/W
UDR
0
INT:
The INT bit indicates when the XFDL is ready to accept a new data byte for
transmission. The INT bit is set to a logic 1 when the previous byte in the
XFDL Transmit Data register has been loaded into the parallel to serial
converter and a new byte can be written into the XFDL Transmit Data register.
The INT bit is set to a logic 0 while new data is in the Transmit Data register.
The INT bit is not disabled by the INTE bit in the configuration register.
UDR:
The UDR bit indicates when the XFDL has underrun the data in the XFDL
Transmit Data register. The UDR bit is set to a logic 1 if the parallel to serial
conversion of the last byte in the XFDL Transmit Data register has completed
before the new byte was written into the XFDL Transmit Data register. Once
an underrun has occurred, the XFDL transmits an ABORT, followed by a flag,
and waits to transmit the next valid data byte. If the UDR bit is still set after
the transmission of the flag the XFDL will continuously transmit the all-ones
idle pattern. The UDR bit can only be cleared by writing a logic 0 to the
UDR bit position in this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
133
PMC [ PMC-SIERRA, INC ]
