PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
Registers 015H, 115H, 215H and 315H: ALMI Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
FASTD
Reserved
YELE
X
X
X
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
REDE
AISE
These registers select which of the three T1 Carrier Failure Alarms (CFA) can
generate an interrupt when their logic state changes and enables the "fast"
deassertion mode of operation.
FASTD:
The FASTD bit enables the "fast" deassertion of red and AIS alarms. When
FASTD is set to a logic 1, deassertion of red alarm occurs within 120 ms of
going in frame. Deassertion of AIS alarm occurs within 180 ms of either
detecting a 60 ms interval containing 127 or more zeros, or going in frame.
When FASTD is set to a logic 0, red and AIS alarm deassertion times remain
as defined in the ALMI description.
Reserved:
The reserved bit must be programmed to logic 0 for correct operation.
YELE,REDE,AISE:
A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state
change in the corresponding CFA to generate an interrupt; a logic 0 in the
enable bit positions disables any state changes to generate an interrupt. The
enable bits are independent; any combination of yellow, red, and AIS CFA's
can be enabled to generate an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
101
PMC [ PMC-SIERRA, INC ]
