PM7344 S/UNI-MPH
DATA SHEET
PMC-950449
ISSUE 6
MULTI-PHY USER NETWORK INTERFACE
high causes the S/UNI-MPH to drive the data bus and holding the CSB pin
low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The
DBCTRL bit is used to measure the drive capability of the data bus driver
pads.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each block in the S/UNI-MPH for board
level testing. When IOTST is a logic 1, all blocks are held in test mode and
the microprocessor may write to a block's test mode 0 registers to manipulate
the outputs of the block and consequently the device outputs (refer to the
"Test Mode 0 Details" in the "Test Features" section).
HIZIO,HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-MPH .
While the HIZIO bit is a logic 1, all output pins of the S/UNI-MPH except the
data bus are held in a high-impedance state. The microprocessor interface is
still active. While the HIZDATA bit is a logic 1, the data bus is also held in a
high-impedance state which inhibits microprocessor read cycles.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PMC [ PMC-SIERRA, INC ]
