PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
10.2.3.4
Timing Reference Link Maintenance
It is possible to have the timing reference link for an IMA group change from one
link to another while the IMA connection is in operation. If an IMA group is
operating in CTC mode, the reference link used for the scheduling is simply
switched. The next stuff cell insertion still occurs 2049 cells after the previous
stuff. If the IMA group is operating in ITC mode and the reference link is
switched, the first stuff insertion on the new TRL occurs at approximately the
same frame a stuff would have been inserted had it not become the TRL. At the
time of the TRL change, the existing accrued rate differential on the new TRL is
used to prorate the number of cells out of 2048 until the next TRL stuff. Although
the first stuff will occur at approximately the proper number of cells to maintain
the correct differential delay, the actual time of the stuff will be dependent on the
new TRL rate.
Similarly, the first stuff cell insertion on the previous TRL occurs in approximately
the same frame a stuff cell would have been inserted had it still been the TRL
although the actual frame for stuff insertion will also be dependent on the rate
difference with the new TRL. This minimizes any effects on the differential delay
for the group as well as reducing any FIFO level changes. All subsequent stuff
cell insertions on the TRL then happen after every 2048 cells and all subsequent
stuff cell insertions on the former TRL are dependent only on the link’s rate
difference from the new TRL.
10.2.4 Receive IMA Data Processor (RDAT)
The Receive IMA Data Processor (RDAT) performs the IMA data-flow functions in
the receive direction including the IMA Frame Synchronization Mechanism
(IFSM), storage of data for accommodating differential delay, defect detection,
and playout of data in a round robin fashion.
One 16 Mbit (1 Mbit x 16) SDRAM, available as a single chip device, is required.
Differential-delay tolerance may be configured through registers on a per-group
basis to any value up to a maximum of 279 msec for T1 or 226 msec for E1.
Buffering is allocated on a per link basis. Each link is allocated 1024 cell buffers.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
