PM7340 S/UNI-IMA-8
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
11.1 Global and Interrupt Registers
Register 0x000: Global Reset
Bit
Type
Function
Default
15
14
13:7
6:4
R/W
RO
RESET
BIST_DONE
Unused
1
X
0
000
RO
RO
TYPE[2:0]
3:0
ID[3:0]
0
ID[3:0]:
The ID bits can be read to provide a binary number indicating the S/UNI-IMA-
8 feature version. These bits are incremented only if features are added in a
revision of the chip.
TYPE[2:0]:
The TYPE bits can be read to distinguish the S/UNI-IMA-8 from the other
members of the S/UNI-IMA-8 family of devices. The S/UNI-IMA-8 is identified
by a value of “001”.
BIST_DONE
The BIST_DONE indicates when the internal ram initialization is complete.
Once the ram initialization is complete, the rams may be accessed. Prior to
BIST_DONE transitioning to a “1”, any ram accesses are ignored.
RESET:
The RESET bit implements a software reset for the entire S/UNI-IMA-8. If the
RESET bit is a logic 1, the entire S/UNI-IMA-8 is held in reset except for the
microprocessor interface. While in reset, the only register that is accessible is
the Global Reset register. This bit is not self-clearing; therefore, a logic 0
must be written to bring the S/UNI-IMA-8 out of reset. Holding the S/UNI-IMA-
8 in a reset state effectively puts it into a low power, stand-by mode. A
hardware reset sets the RESET bit, thus asserting the software reset.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
98
PMC [ PMC-SIERRA, INC ]
