S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Pin Name
Type
Pin No Function
Output Cell/Packet Interface (49 Pins)
This interface can work in one of four different modes:
Mode A (ingress UL3 slave output): Rx PHY Layer UTOPIA L3 interface (prefix: RPU_*)
Mode B (egress UL3 master output): Tx Link Layer UTOPIA L3 interface (prefix: TLU_*)
Mode C (ingress PosPhy 3 output): Rx PHY Layer PosPhy L3 interface (prefix: RPP_*)
Mode D (egress PosPhy 3 output): Tx Link Layer PosPhy L3 interface (prefix: TLP_*)
One of these four modes may be chosen in software. The choice of mode is static is must not be changed during
chip operation. The easiest way to read the table below is to pick a mode of operation (A,B,C, or D) and to read
only those lines that pertain to the chosen mode.
Each pin also has a generic name, which may be used to reference the pin diagrams.
OCIF_CLK
Input
(A) RPU_CLK
(A) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz
(B) TLU_CLK
(C) RPP_CLK
(D) TLP_CLK
(B) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz
(C) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz
(D) Clock. Valid frequency is 75 to 104 MHz. All signals on this
interface are sampled at the rising edge of this clock. Full OC-48c
bandwidth is guaranteed only for 104 MHz
OCIF_DAT[31:0]
Output
(A) RPU_DAT[31:0]
(A) 32-bit data bus. Data path for data from the S/UNI-ATLAS-
3200 to the Traffic Manager/Fabric. RPU_DAT[31] is the MSB
and RPU_DAT[0] is the LSB.
(B) TLU_DAT[31:0]
(C) RPP_DAT[31:0]
(B) 32-bit data bus. Data path for data from the S/UNI-ATLAS-
3200 to the PHY. TLU_DAT[31] is the MSB and TLU_DAT[0] is
the LSB.
(C) 32-bit data bus. The RPP_DAT[31:0] bus carries the packet
octets that are read from the receive FIFO and the in-band port
address of the selected receive FIFO. RPP_DAT[31:0] is
considered valid only when RPP_VAL is asserted
When RPP_SX is asserted, RPP_DAT[7:0] contains the in-band
port address, and RPP_DAT[31:24] optionally carries the
Payload Type field identifying the packet as ATM or POS.
RPP_DAT[31] is the most significant bit.
(D) TLP_DAT[31:0]
(D) 32-bit data bus. This bus carries the packet octets that are
written to the selected transmit FIFO and the in-band port
address to select the desired transmit FIFO. The TLP_DAT bus
is considered valid only when TLP_ENB is simultaneously
asserted.
When TLP_SX is asserted, TLP_DAT[7:0] contains the in-band
port address, and TLP_DAT[31:24] optionally carries the Payload
Type field identifying the packet as ATM or POS.
TLP_DAT[31] is the most significant bit.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
53
PMC [ PMC-SIERRA, INC ]
