S/UNI®-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Register 0x107: AIS/CC Pacing and Head of Line Blocking
Bit
31
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23
22
21
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19
18
17
16
15
14
13
12
11
10
9
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default
AISCCTO[15]
AISCCTO[14]
AISCCTO[13]
AISCCTO[12]
AISCCTO[11]
AISCCTO[10]
AISCCTO[9]
AISCCTO[8]
AISCCTO[7]
AISCCTO[6]
AISCCTO[5]
AISCCTO[4]
AISCCTO[3]
AISCCTO[2]
AISCCTO[1]
AISCCTO[0]
AISCCP[15]
AISCCP[14]
AISCCP[13]
AISCCP[12]
AISCCP[11]
AISCCP[10]
AISCCP[9]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
8
7
6
5
4
3
2
1
AISCCP[8]
AISCCP[7]
AISCCP[6]
AISCCP[5]
AISCCP[4]
AISCCP[3]
AISCCP[2]
AISCCP[1]
0
AISCCP[0]
AISCCP[15:0]
AISCCP[15:0] sets the number of cell intervals between the insertion of consecutive AIS or
CC cells into the cell stream. The minimum rate of transfer is 1 in 65535 cell intervals.
When AISCCP[15:0] = 0x0000 back-to-back AIS or CC cells are possible, if there are no
cells from the Input Cell Interface or the Microprocessor Cell Interface. The default is set to
1 in 32 cell intervals.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
211
PMC [ PMC-SIERRA, INC ]
