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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM73123-PI的Datasheet PDF文件第42页浏览型号PM73123-PI的Datasheet PDF文件第43页浏览型号PM73123-PI的Datasheet PDF文件第44页浏览型号PM73123-PI的Datasheet PDF文件第45页浏览型号PM73123-PI的Datasheet PDF文件第47页浏览型号PM73123-PI的Datasheet PDF文件第48页浏览型号PM73123-PI的Datasheet PDF文件第49页浏览型号PM73123-PI的Datasheet PDF文件第50页  
RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
Pin Name  
Type  
Pin No.  
AB13  
Function  
ALE  
Input  
The address latch enable signal (ALE)  
latches the A[19:0] signals during the  
address phase of a bus transaction. When  
ALE is set high, the address latches are  
transparent. When ALE is set low, the  
address latches hold the address provided  
on A[19:0].  
ALE has an internal pull-up resistor.  
WRB  
Input  
AA13  
The write strobe signal (WRB) qualifies write  
accesses to the AAL1gator-8 device. When  
CSB is set low, the D[15:0] bus contents are  
clocked into the addressed register on the  
rising edge of WRB.  
Note that if CSB, WRB and RDB are all low,  
all chip outputs are tristated. Therefore  
WRB and RDB should never be active at the  
same time during functional operation.  
RDB  
Input  
Y13  
The read strobe signal (RDB) qualifies read  
accesses to the AAL1gator-8 device. When  
CSB is set low, the AAL1gator-8 device  
drives the D[15:0] bus with the contents of  
the addressed register on the falling edge of  
RDB.  
Note that if CSB, WRB and RDB are all low,  
all chip outputs are tristated. Therefore  
WRB and RDB should never be active at the  
same time during functional operation.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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