RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
9.4
PROCESSOR INTERFACE BLOCK (PROCI)........................... 151
9.4.1 INTERRUPT DRIVEN ERROR/STATUS REPORTING.. 156
9.4.2 ADD QUEUE FIFO ......................................................... 159
RAM INTERFACE BLOCK (RAMI)............................................ 161
LINE INTERFACE BLOCK (AAL1_LI) ....................................... 162
9.6.1 CONVENTIONS.............................................................. 162
9.6.2 FUNCTIONAL DESCRIPTION........................................ 162
9.6.3 TRANSMIT DIRECTION................................................. 167
JTAG TEST ACCESS PORT ..................................................... 171
9.5
9.6
9.7
10
MEMORY MAPPED REGISTER DESCRIPTION ................................ 172
10.1 INITIALIZATION ........................................................................ 173
10.2 A1SP AND LINE CONFIGURATION STRUCTURES................ 173
10.2.1 HS_LIN_REG.................................................................. 174
10.3 TRANSMIT STRUCTURES SUMMARY.................................... 179
10.3.1 P_FILL_CHAR ................................................................ 181
10.3.2 T_SEQNUM_TBL ........................................................... 181
10.3.3 T_COND_SIG................................................................. 182
10.3.4 T_COND_DATA.............................................................. 184
10.3.5 RESERVED (TRANSMIT SIGNALING BUFFER)........... 185
10.3.6 T_OAM_QUEUE............................................................. 186
10.3.7 T_QUEUE_TBL .............................................................. 187
10.3.8 RESERVED (TRANSMIT DATA BUFFER) ..................... 200
10.4 RECEIVE DATA STRUCTURES SUMMARY ............................ 201
10.4.1 R_OAM_QUEUE_TBL.................................................... 203
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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