RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Field (Bits)
Description
CLK_SOURCE_TX Selects TL_CLK source. This value will override the
setting defined by the TLCLK_OUTPUT_EN input. If
switching from an external to an internal clock or visa
(6:4)
versa, make sure there are not two clocks driving
simultaneously.
In Direct Low Speed mode all options are valid. In high
speed mode the only valid options are “000” and “001”.
The field is ignored in H-MVIP mode.
000 Use external clock. (TL_CLK is an input).
001 LOOPED – Use RL_CLK as the clock source.
010 NOMINAL Synthesized – Generate a clock of the
nominal (T1 or E1) frequency from SYS_CLK.
011 SRTS Synthesized- Generate a T1/E1 clock
frequency based on the received SRTS values.
100) ADAPTIVE Synthesized- uses receive buffer depth
to generate a T1/E1 clock.
101) Externally controlled Synthesized: Generate a
T1/E1 clock frequency based on the values provided by
CGC_SER_D pin. This mode is used for external
implementations of SRTS or Adaptive clocking.
110) Use common external clock (CTL_CLK) (only valid
in low speed mode)
111) If in Direct Low Speed Mode, use common external
clock (CTL_CLK) and drive TL_SIG data onto TL_CLK
pin.
CLK_SOURCE_RX Selects RL_CLK source.
(3)
0
1
Use external clock. (RL_CLK is an input).
Use common external clock (CRL_CLK) as the
clock source.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
178
PMC [ PMC-SIERRA, INC ]
