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PM73123-PI 参数 Datasheet PDF下载

PM73123-PI图片预览
型号: PM73123-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 8 LINK CES / DBCES AAL1 SAR [8 LINK CES/DBCES AAL1 SAR]
分类和应用:
文件页数/大小: 364 页 / 2908 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM73123 AAL1GATOR-8  
DATASHEET  
PMC-2000097  
ISSUE 2  
8 LINK CES/DBCES AAL1 SAR  
Figure 51 DBCES Receive Side Buffering  
Buffer Depth in Frames  
70  
60  
50  
40  
Buffer Depth in  
Frames  
30  
20  
10  
0
0
5000  
10000  
15000  
20000  
25000  
Time (us)  
9.2.2.2.11  
Counters and Sticky Bits  
The RALP sets sticky bits for overrun, underrun, pointer mismatch, resume,  
SRTS underrun, SRTS resume, and other conditions. As with most registers, the  
sticky bits are located in the external RAM. They are set by the AAL1gator-8 and  
must be cleared by the microprocessor. Sticky bits provide a history of events  
that have occurred. Since these bits can be set with every cell, it is better to use  
the counters for statistics gathering purposes. The AAL1gator-8 increments the  
counters for incorrect SNs, incorrect SNPs, cells received, underflows, overflows,  
dropped cells, misinserted cells, lost cells, pointer parity errors, and pointer  
mismatches. The transfer status bits can be used to detect that a clear was  
overwritten by toggling transfer bit 15 with each clear of the status bits and then  
reading the value immediately thereafter. Refer to “R_ERROR_STKY Word  
Format” for a description of sticky bits.  
The first time that a sticky bit is set for a queue that has the corresponding  
enable bit set in the RCV_STAT_EN_REG register, an entry will be made in the  
RCV_STAT_FIFO containing the queue number and the sticky bit which was just  
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL  
132  
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