PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
The transmit side supports SRTS only for unstructured data formats on a per-line basis. SRTS
support requires an input reference clock, N_CLK. The input reference frequency is defined as
155.52/2^n MHz, where n is chosen such that the reference clock frequency is greater than the
frequency being transmitted, but less than twice the frequency being transmitted (2 × RL_CLK >
N_CLK > RL_CLK). For T1 or E1 implementation, the input reference clock frequency must be
2.43 MHz. The transmit side can accept a reference clock speed of up to 78 MHz, which is
required for T3 applications. Figure 22 on page 33 shows the process implemented for each UDF
line enabled for SRTS, regardless of the reference frequency. The resulting 4-bit SRTS code is
then inserted into the CSI bit of the odd numbered cells for that line. If the line does not supply
SRTS, then all odd CSI bits are set to 0. The 3008 divider is the number of data bits in eight cells
(8 × 8 × 47). The divider is aligned on the first cell generation after a reset or a resynchronization
to the cell generation process.
Server Clock Frequency
4-bit SRTS Code
RL_CLK
Latch
4-Bit Latch
Divide By 3008
4 Bits
Reset
Arm
Cell Generation
4 Bits
Input Reference Clock Frequency
N_CLK
Resync
(For T1/E1, 2.43 MHz. For T3, 77.76 MHz.)
4-Bit Counter
Figure 22. Transmit Side SRTS Support
3.2 Cell Service Decision (CSD) Circuit
The CSD circuit determines which cells are to be sent and when. It determines this by implement-
ing Transmit Calendar bit tables. When the TALP builds a cell, the CSD circuit performs a com-
plex calculation using credits to determine the frame in which the next cell from that queue should
be sent. The CSD circuit schedules a cell only when a cell is built by the TALP. If SUPPRESS_
TRANSMISSION bit in the IDLE_CONFIG word is set, then the cell is scheduled, however, the
cell is not transmitted.
The following steps (as well as Figure 23 on page 35) describe how the CSD circuit schedules
cells for the TALP to build.
1. Once the TFTC writes a complete frame into external memory, it writes the line number and
frame number of this frame into the FR_ADVANCE_FIFO. The CSD circuit reads the
line-frame number pair from the FR_ADVANCE_FIFO and uses it as an index into the Trans-
mit Calendar. The Transmit Calendar is composed of eight-bit tables, one per line. Each bit
table consists of 128 entries, one per frame buffer. Each entry consists of 32 bits, one per
queue. For each bit set in the indexed entry in the Transmit Calendar, the CSD will schedule
the frame in which the next cell can be built for the corresponding queue, and notify the TALP
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PMC [ PMC-SIERRA, INC ]
