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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
7.8.4 R_SRTS_CONFIG  
Organization: 2 bytes × 8 lines  
Base address: 0 8038h  
Index: 1h  
Type: Read/Write  
Function: This table stores the CDVT for the SRTS channel, expressed in the number of  
queued SRTS nibbles.  
Initialization: Initialize to the number of SRTS nibbles equivalent to the CDVT for the  
data by rounding up. Each frame of CDVT for unstructured applications represent 256  
bits. Each SRTS nibble represents 3008 bits, which is the number of data bits in eight  
cells. Therefore, the number of SRTS nibbles that corresponds to the CDVT can be  
determined by dividing the CDVT number in frames by 3008 ÷ 256, or 11.75, and  
rounding up to the next higher integer.  
Format: One byte per line. Refer to the following table.  
Offset  
Name  
Description  
Receive SRTS CDVT for line 0.  
0h  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
R_SRTS_CDVT_0  
R_SRTS_CDVT_1  
R_SRTS_CDVT_2  
R_SRTS_CDVT_3  
R_SRTS_CDVT_4  
R_SRTS_CDVT_5  
R_SRTS_CDVT_6  
R_SRTS_CDVT_7  
Receive SRTS CDVT for line 1.  
Receive SRTS CDVT for line 2.  
Receive SRTS CDVT for line 3.  
Receive SRTS CDVT for line 4.  
Receive SRTS CDVT for line 5.  
Receive SRTS CDVT for line 6.  
Receive SRTS CDVT for line 7.  
R_SRTS_CDVT_n Word Format  
Field (Bits)  
Description  
Not used  
(15:5)  
Write with 0 to maintain compatibility with future software versions.  
R_SRTS_CDVT  
(4:0)  
Receive SRTS CDVT.  
ꢀꢃꢄ  
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