PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
9.4.3 CRC Check and AIS Detection
The CRC Check and AIS Detect Block computes the 4-bit CRC checksum for
each incoming sub-multiframe and compares this 4-bit result to the received
CRC remainder bits in the subsequent sub-multiframe. The block also
accumulates CRC errors over 1 second intervals, monitoring for excessive CRC
errors and optionally, forcing the Frame Find Block to initiate a frame search
when ≥ 915 CRC errors occur in 1 second. The number of CRC errors
accumulated during the previous second is available by reading the FRMR CRC
Error Counter Registers.
The block also detects the occurrence of an unframed all-ones receive data
stream, indicating the AIS by setting the AISD indication when less than 3 zero
bits are received in 2 frames (512 consecutive bits); the AISD indication is reset
when 3 or more zeros in the E1 stream are observed, or when frame alignment is
found.
9.4.4 Signalling Frame Find
Once the basic frame alignment has been found, the Signalling Frame Find Block
searches for CAS multiframe alignment using one of two user-selectable
algorithms, one of which is compatible with Recommendation G.732. Once
frame alignment has been found, the first algorithm monitors timeslot 16 of each
frame; it declares CAS multiframe alignment when 15 consecutive frames with
bits 1-4 of timeslot 16 not containing the alignment pattern are observed to
precede a frame with timeslot 16 containing the correct alignment pattern. The
second algorithm, compatible with G.732, also monitors timeslot 16 of each
frame, and declares CAS multiframe alignment when non-zero bits 1-4 of
timeslot 16 are observed to precede a timeslot 16 containing the correct
alignment pattern.
Once CAS multiframe alignment has been found, the block sets the OOSMF
indication to logic 0, and monitors the CAS multiframe alignment signal,
indicating errors occurring in the 4-bit pattern, and indicating the debounced
value of the remote signalling multiframe alarm bit (bit 6 of timeslot 16 of frame 0
of the multiframe). Using debounce, the remote signalling multiframe alarm bit
has
-3
< 0.00001% probability of being falsely indicated in the presence of a 10 bit
error rate. This block also indicates the reception of timeslot 16 AIS when
timeslot 16 has been all-ones for two consecutive frames while out of CAS
multiframe. The block declares loss of CAS multiframe alignment if two
consecutive CAS multiframe alignment signals have been received in error, or
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
48
PMC [ PMC-SIERRA, INC ]
