PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Channel associated signalling insertion, idle code substitution, digital milliwatt
tone substitution, and data inversion on a per-timeslot basis is also supported.
Transmit side data and signalling trunk conditioning is provided.
HDLC messages on a data link can be transmitted. The data link may be
inserted into timeslot 16 and used for common channel signalling or may be
inserted into the national bits. The E1XC can generate a low jitter transmit clock
and provides a FIFO for transmit jitter attenuation. When not used for jitter
attenuation, the full or empty status of this FIFO is made available to facilitate
higher order multiplexing applications by controlling bit-stuffing logic.
Interfaces include both a parallel microprocessor port for controlling the
operation of the device and a serial PCM interface that allows 2048 kbit/s
backplanes to be directly supported. Tolerance of gapped clocks allows other
backplane rates to be supported with a minimum of external logic.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
PMC [ PMC-SIERRA, INC ]
