PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Figure 36
- Microprocessor Read AccessTiming
tS
AR
A[7:0]
ALE
Valid
Address
tH
AR
tS
ALR
tV
tH
L
ALR
tH
tS
LR
LR
(CSB+RDB)
INTB
tP
INTH
tZ
tP
RD
RD
Valid Data
D[7:0]
Notes on Microprocessor ReadTiming:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 50 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. Microprocessor Interface timing applies to normal mode register accesses
only.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
232
PMC [ PMC-SIERRA, INC ]
