PMC-Sierra, Inc.
STANDARD PRODUCT
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
APP_SAPI_UTP5
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Figure 5: Microprocessor Interface Read Timing
A[8:0]
Valid Address
tH
tS
AR
AR
(CSB+RDB)
INTB
tP
INTL
tP
tZ
RD
RD
Valid Data
D[7:0]
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 50% point of
the reference signal to the 30% or 70% point of the output.
2. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
3. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
4.
When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of
the clock.
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PMC [ PMC-SIERRA, INC ]
