PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0746H: RCFP Idle Cell Header and Mask
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[3]
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PTI[2]
PTI[1]
Bit 8
CLP
Bit 7
MGFC[3]
MGFC[2]
MGFC[1]
MGFC[0]
MPTI[3]
MPTI[2]
MPTI[1]
MCLP
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLP:
The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell.
This mask is applied to this register to select the bits included in the cell filter. Logic 1 in this
bit position enables the CLP bit in the pattern register to be compared. Logic 0 causes the
masking of the CLP bit. The default enables the register bit comparison.
MPTI[3:0]:
The MPTI[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth
octet of the 53-octet cell. This mask is applied to the Idle Cell Header field to select the bits
included in the cell filter. A logic 1 in any bit position enables the corresponding bit in the
pattern register to be compared. A logic 0 causes the masking of the corresponding bit. The
default enables the register bit comparison.
MGFC[3:0]:
The MGFC[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the
first octet of the 53-octet cell. This mask is applied to the Idle Cell Header field to select the
bits included in the cell filter. Logic 1 in any bit position enables the corresponding bit in the
pattern register to be compared. Logic 0 causes the masking of the corresponding bit. The
default enables the register bit comparison.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
317
PMC [ PMC-SIERRA, INC ]
