PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
CRC_SEL[1:0]:
The CRC select (CRC_SEL[1:0]) bits allow the control of the CRC calculation according to
the table below. For ATM cells, the CRC is calculated over the first four ATM header bytes.
For packet applications, the CRC is calculated over the whole packet data, after byte
destuffing and descrambling.
Table 9: Functionality of the CRC_SEL[1:0] register bits
CRC_SEL[1:0]
HCS Operation
FCS Operation
00
01
10
11
Reserved
No FCS verification
Reserved
Reserved
CRC-8 without coset polynomial
CRC-8 with coset polynomial added
CRC-CCITT (2 bytes)
CRC-32 (4 bytes)
CRCPASS:
The CRCPASS bit controls the dropping of cells and packets based on the detection of a
CRC error.
When in ATM mode and when CRCPASS is a logic 0, cells containing an uncorrectable HCS
error are dropped and the HCS verification state machine transitions to the 'Detection Mode'.
Cells containing a correctable HCS error have the error fixed (if HCS error correction is
enabled), and the state machine transitions to the 'Detection Mode'.
When CRCPASS is logic 1, cells are passed to the external FIFO interface regardless of
errors detected in the HCS. Additionally, the HCS verification finite state machine will never
lose cell delineation.
Regardless of the programming of this bit, ATM cells are always dropped while the cell
delineation state machine is in the 'HUNT' or 'PRESYNC' states unless the DELINDIS bit in
this register is set to logic 1.
When in POS mode and CRCPASS is logic 1, then packets with FCS errors are not marked
as such and are passed to the external FIFO interface as if no FCS error occurred. When
CRCPASS is logic 0, then packets with FCS errors are marked with ERR.
IDLEPASS:
The IDLEPASS bit controls the function of the ATM Idle Cell filter. It is only valid when in ATM
mode. When IDLEPASS is written with logic 0, all cells that match the Idle Cell Header
Pattern and Idle Cell Header Mask are filtered out. When IDLEPASS is enabled, the Idle Cell
Header Pattern and Mask register bits are ignored. The default state of this bit and the bits in
the RCFP Idle Cell Header and Mask Register enable the dropping of Idle cells.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
308
PMC [ PMC-SIERRA, INC ]
