PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
IADDR[7:0]:
The indirect address location (IADDR[7:0]) bits select which indirect address location is
accessed by the current indirect transfer.
Indirect Address
Indirect Data
IADDR[7:0]
0000 0000
Configuration
0000 0001
to
Invalid address
0011 1111
0100 0000
First byte of the 1/16/64 byte captured trace
Other bytes of the 16/64 byte captured trace
0100 0001
to
0111 1111
1000 0000
First byte of the 1/16/64 byte accepted trace
Other bytes of the 16/64 byte accepted trace
1000 0001
to
1011 1111
1100 0000
First byte of the 16/64 byte expected trace
Other bytes of the 16/64 byte expected trace
1100 0001
to
1111 1111
RWB:
The active high read and active low write (RWB) bit selects if the current access to the
internal RAM is an indirect read or an indirect write. Writing to the Indirect Address Register
initiates an access to the internal RAM. When RWB is set to logic 1, an indirect read access
to the RAM is initiated. The data from the addressed location in the internal RAM will be
transferred to the Indirect Data Register. When RWB is set to logic 0, an indirect write access
to the RAM is initiated. The data from the Indirect Data Register will be transferred to the
addressed location in the internal RAM.
BUSY:
The active high RAM busy (BUSY) bit reports if a previously initiated indirect access to the
internal RAM has been completed. BUSY is set to logic 1 upon writing to the Indirect Address
Register. BUSY is set to logic 0, upon completion of the RAM access. This register should
be polled to determine when new data is available in the Indirect Data Register.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
182
PMC [ PMC-SIERRA, INC ]
