S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x00D, 0x10D, 0x20D, 0x30D, 0x40D, 0x50D, 0x60D, 0x70D:
Channel Receive Path AIS Control
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PAISCONPAIS
LOPCONPAIS
PSLUPAIS
PSLMPAIS
LOPPAIS
Reserved
TIUPAIS
TIMPAIS
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
This register controls the auto assertion of path AIS, which will force a loss of cell delineation
by the receive cell processor.
TIMPAIS:
When set high, the TIMPAIS bit enables path AIS insertion when path trace message
mismatch (TIM) events are detected in the receive stream. When TIMPAIS is set low, trace
identifier mismatch events will not assert path AIS.
TIUPAIS:
When set high, the TIUPAIS bit enables path AIS insertion when path trace message
unstable events are detected in the receive stream. When TIUPAIS is set low, trace
identifier unstable events will not assert path AIS.
LOPPAIS:
When set high, the LOPPAIS bit enables path AIS insertion when loss of pointer (LOP)
events are detected in the receive stream. When LOPPAIS is set low, loss of pointer events
will not assert path AIS.
PSLMPAIS:
When set high, the PSLMPAIS bit enables path AIS insertion when path signal label
mismatch (PSLM) events are detected in the receive stream. When PSLMPAIS is set low,
path signal label mismatch events will not assert path AIS.
PSLUPAIS:
When set high, the PSLUPAIS bit enables path AIS insertion when path signal label
unstable (PSLU) events are detected in the receive stream. When PSLUPAIS is set low,
path signal label unstable events will not assert path AIS.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
137
PMC [ PMC-SIERRA, INC ]
