S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x007, 0x107, 0x207, 0x307, 0x407, 0x507, 0x607, 0x707:
Channel Master Interrupt Status #2
Bit
Type
R
R
R
R
R
R
R
R
Function
JATI
DCRUI
CRSII
TXFPI
RXFPI
WANSI
SSTBI
SPTBI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
When the interrupt output INTB goes low, this register allows the source of the active interrupt
to be identified down to the block level for the channel. Further register accesses are required
for the block in question to determine the cause of an active interrupt and to acknowledge the
interrupt source.
In addition, writing to this register simultaneously loads all the performance monitor registers in
the channel. The corresponding channel CHTIP bit (registers 0x004, 0x104, 0x204, 0x304,
0x404, 0x504, 0x604, 0x704) is set high while the performance registers are loaded and clears
when the transfer is done.
SPTBI:
The SPTBI bit is a logic one when an interrupt request is active from the SPTB block. The
SPTB interrupt sources are enabled in the SPTB Control Register and the SPTB Path Signal
Label Status Register.
SSTBI:
The SSTBI bit is a logic one when an interrupt request is active from the SSTB block. The
SSTB interrupt sources are enabled in the SSTB Control Register and the SSTB
Synchronization Message Status Register.
WANSI:
The WANSI bit is a logic one when an interrupt request is active from the WANS block.
The WANS interrupt sources are enabled in the WANS Interrupt Enable/Status Register.
RXFPI:
The RXFPI bit is high when an interrupt request is active from the RXFP block. The RXFP
interrupt sources are enabled in the RXFP Interrupt Enable/Status Register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
124
PMC [ PMC-SIERRA, INC ]
