S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
RASEI:
The RASEI bit is high when an interrupt request is active from the RASE block. The RASE
interrupt sources are enabled in the RASE Interrupt Enable Register.
CONCATI:
The CONCATI bit is high when an interrupt request is active from the Concatenation
Interrupt Status Register. The CONCAT interrupt sources are enabled in the Concatenation
Status and Enable Register.
CHRST:
The CHRST bit allows the channel to be reset under software control. If the CHRST bit is a
logic one, the entire channel is held in reset. This bit is not self-clearing. Therefore, a logic
zero must be written to bring the channel out of reset. Holding the channel in a reset state
places it into a low power, stand-by mode. A hardware reset or top level reset using RESET
clears the CHRST bit, thus negating the software reset. Otherwise, the effect of the channel
software reset is equivalent to that of a hardware reset.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
123
PMC [ PMC-SIERRA, INC ]
