S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x006, 0x106, 0x206, 0x306, 0x406, 0x506, 0x606, 0x706:
Channel Reset/Master Interrupt Status #1
Bit
Type
R/W
R
R
R
R
R
R
R
Function
CHRST
CONCATI
RASEI
TXCPI
RXCPI
RPOPI
RLOPI
RSOPI
Default
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
When the interrupt output INTB goes low, this register allows the source of the active interrupt
to be identified down to the block level for the channel. Further register accesses are required
for the block in question to determine the cause of an active interrupt and to acknowledge the
interrupt source.
RSOPI:
The RSOPI bit is high when an interrupt request is active from the RSOP block. The RSOP
interrupt sources are enabled in the RSOP Control/Interrupt Enable Register.
RLOPI:
The RLOPI bit is high when an interrupt request is active from the RLOP block. The RLOP
interrupt sources are enabled in the RLOP Interrupt Enable/Status Register.
RPOPI:
The RPOPI bit is high when an interrupt request is active from the RPOP block. The RPOP
interrupt sources are enabled in the RPOP Interrupt Enable Register.
RXCPI:
The RXCPI bit is high when an interrupt request is active from the RXCP block. The
RXCP interrupt sources are enabled in the RXCP Interrupt Enable/Status Register.
TXCPI:
The TXCPI bit is high when an interrupt request is active from the TXCP block. The TXCP
interrupt sources are enabled in the TXCP Interrupt Control/Status Register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
122
PMC [ PMC-SIERRA, INC ]
