Advance
PM5376
TSE-Nx160
• Interfaces to STS-192 devices over a
set of four links.
• Interfaces to STS-768 devices over a
set of sixteen links.
• Interfaces to the ARROW family of
framers and the TBS-9953 in scaled
fabrics.
Transmission Switch Element
FEATURES
SWITCHING CAPACITY
• Implements a 64-port memory switch
fabric with STS-1/AU-3 switching
granularity and scaling capability in a
single device.
• With a set of four devices, implements
a 640G 256-port single-stage switch
fabric. With a set of two devices,
implements a 320G 128-port single-
stage switch fabric.
• Supports non-blocking anycast
switching in all single stage
configurations.
• Supports fabric capacities greater than
640G using multi-stage fabrics.
• Provides two pages of connection
memory with software and hardware
controlled hitless page swaps at frame
boundaries.
• Supports trunk conditioning on a per
port, per egress grain basis for AIS and
UNEQ insertion.
SWITCH PORT CONFIGURATION
• Each ingress and egress link can be
individually configured to support STS-
48 or STS-12 equivalent flows using
SONET scrambling over CML links.
• Interfaces to industry standard
SONET/SDH framers for STS-1
granularity byte switching.
CENTRALIZED OVERHEAD
ACCESSIBILITY
• Provides a high bandwidth interface
with insert and extract access to all
TOH bytes from all ports.
• Provides a clock and data interface
where the number of extracted and
inserted TOH bytes is limited to 99
bytes per port selected for each
ingress port.
BLOCK DIAGRAM
R_P[1]
R_N[1]
Data
Receive
Receive
CML Receiver and digital
Recovery
CML
ESSI
I/O functions
Unit
(RXCML)
(RSSI)
(DCRU)
Transmit
Transmit
CML Transmitter and digital
Serializer
ESSI
CML
I/O (PISO)
functions
(TSSI)
(TXCML)
T_P[1]
T_N[1]
R_P[2]
R_N[2]
MEMORY
SWITCH
CORE
T_P[2]
T_N[2]
R_P[63]
R_N[63]
CONNECTION
CONNECTION
MEMORY
MEMORY
T_P[63]
T_N[63]
R_P[64]
R_N[64]
Data
Receive
Receive
Recovery
CML Receiver and digital
CML
ESSI
Unit
I/O functions
(RXCML)
(RSSI)
(DCRU)
Transmit
Transmit
CML Transmitter and digital
Serializer
ESSI
CML
I/O (PISO)
functions
(TSSI)
(TXCML)
T_P[64]
T_N[64]
HB_TOHI_P[1]
HB_TOHI_N[1]
HB_TOHI_P[2]
HB_TOHI_N[2]
HB_TOHI_P[3]
HB_TOHI_N[3]
HB_TOHI_P[4]
HB_TOHI_N[4]
LB_ID[4:1][1:0]
LB_IFP[4:1]
LB_ICLK[4:1]
SYSCLK
RJ0FP
CMPS[A:B]
JTAG
Test Access
Port
Data
Receive
Receive
Recovery
CML TOH Insertion Interface
CML
ESSI
Unit
(RXCML)
(RSSI)
(DCRU)
TOHI
TOHI
TOHI
CSUI
HB_TOHE_P[1]
HB_TOHE_N[1]
HB_TOHE_P[2]
CML TOH Extration Interface
HB_TOHE_N[2]
HB_TOHE_P[3]
HB_TOHE_N[3]
HB_TOHE_P[4]
HB_TOHE_N[4]
LB_EFP[4:1]
LB_ED[4:1][1:0]
LB_ECLK[4:1]
CSU
CSU
CSU
CSU
Microprocessor I/F
MPSA
MPSB
TJ0FPA
TJ0FPB
REFCLK_P[1]
REFCLK_N[1]
REFCLK_P[2]
REFCLK_N[2]
REFCLK_P[3]
REFCLK_N[3]
REFCLK_P[4]
REFCLK_N[4]
PMC-2020819 (A1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ATB3[4:1]
ATB2[4:1]
ATB1[4:1]
ATB0[4:1]
TST[8:1]
TDO
TDI
TMS
TCK
TRSTB
D[15:0]
A[15:0]
ALE
CSB
WRB
RDB
RSTB
INTB
© Copyright PMC-Sierra, Inc. 2002
PMC [ PMC-SIERRA, INC ]
