PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. In Intel mode, a valid read cycle is defined as a logical OR of the CSB and the
RDB signals.
4. In Motorola mode, a valid read cycle is defined as a logical AND of the E
signal, the RWB signal and the inverted CSB signal.
5. Microprocessor Interface timing applies to normal mode register accesses
only.
6. In non-multiplexed address/data bus architectures, ALE should be held high,
parameters tS
, tH , tV , and tS are not applicable.
ALR ALR L LR
7. Parameter tH and tS are not applicable if address latching is used.
AR
AR
8. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
9. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
415
PMC [ PMC-SIERRA, INC ]
