PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
For STM-4-4c bypass, all three tributary payload processors (VTPP) in each of
the four STM-1 (STS-3) tributary processors (STP) must be disabled by setting
the TUGEN bits low. Tributary performance monitoring of the STM-4-4c stream is
not required and is disabled in this bypass configuration.
13.6 Power Sequencing
Due to ESD protection structures in the pads, it is necessary to exercise caution
when powering a device up or down. ESD protection devices behave as diodes
between power supply pins and from I/O pins to power supply pins. Under
extreme conditions, it is possible to damage these ESD protection devices or
trigger latch-up. The recommended power supply sequencing is as follows:
1. To prevent damage to the ESD protection on the device inputs, the maximum DC
input current specification must be respected. This is accomplished by either
ensuring that the VDD/VDDI power is applied before input pins are driven or by
increasing the source impedance of the driver so that the maximum driver short
circuit current is less than the maximum DC input current specification (20 mA).
2. Power supply to the core (VDDI) must be applied after VDD have been applied or
they must be current limited to the maximum latch-up current specification (100 mA).
3. Power down the device in the reverse sequence. Use the above current limiting
technique for the VDDI power supply. Small offsets in VDD and VDDI discharge
times will not damage the device.
13.7 JTAG Support
The TUPP+622 supports the IEEE Boundary Scan Specification as described in
the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five
standard pins, TRSTB, TCK, TMS, TDI and TDO, used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active low
reset signal used to reset the TAP controller. TCK is the test clock used to sample
data on input, TDI and to output data on output, TDO. The TMS input is used to
direct the TAP controller through its states. The basic boundary scan architecture
is shown below.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
382
PMC [ PMC-SIERRA, INC ]
