PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Figure 15
- SDH STM-1 Carrying Mix Of TU11, TU12, TU3 Within
TUG3/AU4
COL
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
268 269 270
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
ROW 1 A1 A1 A1 A2 A2 A2 C1 C1 C1 J1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H1 H1 H1 POH
H2 H2 H2 POH
H3 H3 H3 POH
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPE V4 V4
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
SPE SPE SPE
2
3
4
5
6
7
8
9
B1
D1
-
-
-
-
E1
D2
-
-
-
-
F1
D3
-
-
-
-
B3
C2
H1 H1 H1 H2 H2 H2 H3 H3 H3 G1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
POH
POH
POH
POH
POH
POH
B2 B2 B2 K1
-
-
-
-
-
-
-
-
-
-
K2
D6
-
-
-
-
-
-
-
-
-
-
F2
H4
Z3
Z4
Z5
• • • •
D4
D7
D10
Z1
-
-
-
-
-
-
-
-
D5
D8
D11
Z2
D9
D12
E2
First of 86 columns occupied by
TU3 carried in TUG3 #1 of an
STM-1 stream
First of 3 columns occupied by
TU11 #1 of TUG2 #1 of
Last of 4 columns
occupied by TU12 #3
of TUG2 #7 of TUG3 #3
of an STM-1 stream
TUG3 #2 of an STM-1 stream
(column set is 20, 104, 188)
(column set is 81, 144, 207, 270)
In Figure 15 above, the H1 to H3 byte in column 13 form the TU3 offset pointer.
The H1 to H3 bytes in columns 14 and 15 are null pointer indications (NPI) for
TUG3 #2 and #3.
13.5 Bypass Options
The three tributary payload processors (VTPP) in each of the four STM-1 (STS-3)
tributary processors (STP) in the TUPP+622 may be individually disabled or
bypassed using the corresponding TUGEN or TUGBYP register bits, respectively.
This enables the TUPP+622 to support STS-1/AU3/TUG3 level bypass
operation. Incoming data destined to a disabled or bypassed processor is re-
transmitted unchanged to the outgoing data after some delay. The amount of
delay is fixed when the 19.44 MHz STM-1 interface mode for both the incoming
and outgoing interfaces are selected. When either or both incoming and outgoing
interfaces are set to the 77.76 MHz STM-4 interface mode, the amount of delay
is also dependent on the relative phase of the corresponding incoming frame
pulse (IC1J1) and the GSCLK frame pulse (GSCLK_FP). Figure 26 and Figure
27 show the functional timing of possible bypass delays for the STM-1 (STS-3)
and the STM-4 (STS-12) interface modes, respectively.
For STM-1 (AU4) bypass operation, all three tributary payload processors
(VTPP) of the corresponding STM-1 (STS-3) tributary processor (STP) must be
bypassed by setting the TUGEN and TUGBYP bits high. Tributary performance
monitoring of the STM-1 (AU4) stream remains active in this bypass
configuration.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
381
PMC [ PMC-SIERRA, INC ]
