PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
Register 14H: STP Input Signal Activity Monitor #2
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Reserved
IAISA
ITPLA
ITV5A
HSCLKA
X
X
X
X
X
X
X
X
R/W
R
R
R
R
This register, along with the STP Input Signal Activity Monitor #1, Accumulation
Trigger register, provides activity monitoring on TUPP+622 input signals. When a
monitored input signal makes a low to high transition, the corresponding register
bit is set high. The bit will remain high until this register is read, at which point, all
the bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read periodically to
detect for stuck at conditions.
HSCLKA:
The HSCLK active (HSCLKA) bit monitors for low to high transitions on the
HSCLK input. HSCLKA is set high on a rising edge of HSCLK, and is set low
when this register is read.
ITV5A:
The ITV5 active (ITV5A) bit monitors for low to high transitions on the
corresponding ITV5 input. ITV5A is set high on a rising edge of ITV5, and is
set low when this register is read.
ITPLA:
The ITPL active (ITPLA) bit monitors for low to high transitions on the
corresponding ITPL input. ITPLA is set high on a rising edge of ITPL, and is
set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
159
PMC [ PMC-SIERRA, INC ]
